1. Technical Field
Various embodiments of the present invention relate to semiconductor circuits and related methods thereof. In particular, certain embodiments relate to a refresh control circuit, a memory is apparatus including such refresh control circuit, and a refresh control method using the same.
2. Related Art
A memory apparatus such as a dynamic random access memory (DRAM) apparatus loses data written in its memory cell with the lapse of time due to its structural characteristics. That is, the voltage level of a cell capacitor of the memory apparatus changes.
Therefore a refresh operation must be performed in such a DRAM apparatus to retain the written data, whereby the value of data stored in a memory cell periodically read and restored to its original level.
FIG. 1 is a block diagram of a conventional refresh control circuit 1 in a DRAM apparatus.
As exemplarily illustrated in FIG. 1, a typical refresh control circuit 1 may include a refresh timing control unit 10, an address control unit 20, and a bank control unit 30.
The refresh timing control unit 10 is configured to generate refresh timing signals for determining the timing of a refresh operation in response to an external refresh command AFACT.
The refresh timing signals comprise a refresh period signal REF, an internal refresh command FACT<0:3>, a row access strobe signal IRAS<0:7>, and a precharge signal PRE<0:7>.
The refresh timing control unit 10 includes a plurality of logic circuit units 11 to 17.
The address control unit 20 is configured to generate a is refresh address RA<0:13> in response to the refresh period signal REF.
The address control unit 20 includes a plurality of logic circuit units 21 to 23.
The bank control unit 30 is configured to generate a row active signal RACTV<0:7> in response to the internal refresh command FACT<0:3> and the precharge signal PRE<0:7>.
FIG. 2 is an exemplary circuit diagram of the first logic circuit unit 11 illustrated in FIG. 1.
As shown exemplarily in FIG. 2, the first logic circuit unit 11 may include NAND gates ND1 and ND2 and inverters IV1 and IV2.
The first logic circuit unit 11 sets the refresh period signal REF to a logical high level in response to the external refresh command AFACT, and resets the refresh period signal REF to a logical low level in response to an idle signal IDLE.
FIG. 3 is a timing diagram illustrating an operation of the conventional refresh control circuit 1 illustrated in FIG. 1.
Referring to FIG. 3, the first logic circuit unit 11 generates the refresh period signal REF in response to the external refresh command AFACT and the idle signal IDLE.
The address control unit (CLCFFRF) 20 maintains the refresh address RA<13> at a predetermined logical level, for example, at a logical high level.
The second logic circuit unit (CLREF) 12 generates the internal refresh command FACT<0:3> in response to the refresh is period signal REF.
The third logic circuit unit (PILED_DLY) 13 delays an output signal REFBA of the second logic circuit unit 12 and generates a delay signal REFBAD.
The bank control unit 30 activates the row active signal RACTV<0:7> in response to the internal refresh command FACT<0:3>.
The fourth logic circuit unit 14 generates the idle signal IDLE by NORing the row active signal RACTV<0:7>.
The fifth logic circuit unit 15 generates the row access strobe signal IRAS<0:7> in response to the row active signal RACTV<0:7>.
The sixth logic circuit unit 16 generates a preliminary precharge signal RE<0:3> in response to the row access strobe signal IRAS<0:7> and the refresh period signal REF.
The seventh logic circuit unit 17 generates the precharge signal PRE<0:7> in response to the external refresh command AFACT and the preliminary precharge signal RE<0:3>.
The bank control unit 30 deactivates the row active signal RACTV<0:7> in response to the precharge signal PRE<0:7>.
Word lines of memory banks BA<0, 3, 4, 7> corresponding to the row active signals RACTV<0, 3, 4, 7> and the refresh addresses RA<0:13> are activated, and a charge sharing operation of a bit/bit-bar line BL/BLB<n> is performed accordingly.
According to the operation standards of a memory apparatus, a DRAM apparatus must perform a refresh operation 8K times per 64 msec.
Thus, if the conventional refresh control circuit 1 is designed to be suitable for a DRAM apparatus with a storage density of 4 G (Giga bytes), a row address is 16 bits. Therefore, 8 word lines must be activated in response to one external refresh command AFACT in order to refresh all the memory cells.
Here, a refresh row cycle time (tRFC) is one of the operation standards relevant to a refresh operation of the DRAM apparatus. The refresh row cycle time tRFC is equal to a row active time tRAS+a row precharge time tRP.
In the conventional method, when the external refresh command AFACT is inputted once, eight word lines (one word lines for each of the eight memory banks BA<0:7>) are activated for the refresh row cycle time tRFC with respect to the same refresh address RA<0:13>.
That is, four word lines of the memory banks BA<0, 3, 4, 7> are activated at the same time. Also, four word lines of the memory banks BA<1, 2, 5, 6> are activated at the same time.
The four word lines of the memory banks BA<0, 3, 4, 7> and the four word lines of the memory banks BA<1, 2, 5, 6> have substantially the same activation period with a slight time difference.
Meanwhile, the DRAM apparatus has a fuse set and a repair word line for repairing a defective word line.
Thus, because eight word lines corresponding to the same is row addresses A0 to A13 have substantially the same activation period by one external refresh command AFACT, the entire row region must be divided into 8 regions to perform a word line repair operation. This causes an increase in the number of repair-related circuits, that is, repair word lines and fuse sets.
As described above, according to the conventional method, the area efficiency of repair-related circuits decreases with an increase in the storage density of a memory apparatus, that is, the area of repair-related circuits increases with an increase in the number of fuse sets and repair word lines for a word line repair operation.